Semiconductor device and wiring method thereof

ABSTRACT

Provides a semiconductor device that can separate components easily. Gate electrode  42  is formed only within component forming region  32,  and gate electrode  42  and aluminum wiring  48  are connected in component forming region  32.  Therefore, there is almost no inversion of the surface of the semiconductor substrate  36  that is under field oxide film  38  due to the voltage of the concerned connection area and gate electrode  42.  Also, there is interlayer film  44  between aluminum wiring  48  and field oxide film  38,  so there is almost no inversion of the surface of the semiconductor substrate  36  that is under field oxide film  38  due to the voltage of aluminum wiring  48.  Therefore, it is possible to separate components without increasing overall length L 1  of field oxide film  38,  increasing the film thickness of field oxide film  38,  or increasing the concentration of channel stop ions implanted into the surface of the semiconductor substrate  36  that is under field oxide film  38.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The entire disclosure of Japanese Patent Application No. Hei10-14352 filed on Jan. 27, 1998 including specification, claims,drawings and summary are incorporated herein by reference in itsentirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device, and moreparticularly to a technique for improving the component separatingfunction of a semiconductor device.

[0004] 2. Description of the Related Art

[0005] MOS type field effect transistors (Metal Oxide SemiconductorField Effect Transistor) are known as semiconductor components. FIG. 8is a conceptual figure of a flat structure of a semiconductor devicecomprising conventional MOS type field effect transistors (referred toat times hereafter simply as “transistor”). FIG. 9 shows cross-section9-9 of FIG. 8.

[0006] As shown in FIG. 9, a transistor 12 is formed within thissemiconductor device. The transistor 12 comprises a channel formingregion CH which is sandwiched between source S1 and drain D1 (see FIG.8).

[0007] A gate electrode 22 is formed on the channel forming region CHvia a gate oxide film 20. An interlayer film 24 is formed on the gateelectrode 22. An aluminum wiring 28 is formed on the interlayer film 24.The gate electrode 22 and the aluminum wiring 28 are connected via acontact hole 26 which is formed in the interlayer film 24.

[0008] Another transistor 14 is formed on the semiconductor deviceseparately from the transistor 12 via a field oxide film 18 forcomponent separation. Thus, by interposing the field oxide film 18between the two transistors 12 and 14, it is possible to separate thetransistors electrically.

[0009] However, such conventional semiconductor devices have thefollowing type of problems. As shown in FIG. 9, the contact hole 26 forconnecting the gate electrode 22 and the aluminum wiring 28 is formed onthe field oxide film 18. Therefore, part of the gate electrode 22 of thetransistor 12 is placed directly on top of the field oxide film 18.

[0010] Thus, when a voltage is applied to the gate electrode 22, thereis a possibility of the surface of semiconductor layer 16 (the partshown by the “x” mark in the figure) directly below the field oxide film18 being inverted. There is a particularly high risk for this with highwithstand voltage transistors for which a high voltage is applied to thegate electrode 22. If the surface of the semiconductor layer 16 beneaththe field oxide film 18 is inverted, the inverted portion will notfunction as a component separating region.

[0011] To electrically separate the transistor 12 and the transistor 14to avoid this situation, a sufficiently large length L1 of thenon-inverted part can be secured. However, with this method, the overalllength L2 of the field oxide film 18 becomes long, so the layout spacefor the transistor 12 and the transistor 14 becomes large. This leads toa reduction in the degree of integration of the semiconductor device.

[0012] Another method that can be considered to avoid the problemdescribed above is making the film thickness of the field oxide film 18thick. However, if the overall length L2 of the field oxide film 18 isleft as is and the film thickness is increased, the incline angle of thearea near the edge (bird's beak area) 18 a of the field oxide film 18becomes large, and the degree of concentration of the electrical fieldfor the edge area 18 a becomes larger. This makes it impossible toobtain the desired withstand voltage.

[0013] Also, if the film thickness of the field oxide film 18 isincreased, a greater time is required for forming the field oxide film18, so production efficiency is lowered, and production costs areincreased.

[0014] As a further method for avoiding the problems described above, wecan consider a method of increasing the density of channel stop ionsimplanted into the surface of the semiconductor layer 16 which is underthe field oxide film 18. However, if the density of the channel stopions is increased, there is a decrease in the withstand voltage.

SUMMARY OF THE INVENTION

[0015] An object of the present invention is to provide a semiconductordevice that solves these types of problems and that can separatecomponents easily.

[0016] In accordance with characteristics of the present invention,there is provided a semiconductor device comprising:

[0017] a base semiconductor layer,

[0018] an insulation film for separating components formed on the basesemiconductor layer, and

[0019] a semiconductor component which is formed on the basesemiconductor layer in a component forming region separated by theinsulation film for separating components, the semiconductor componenthaving a first conductive layer,

[0020] wherein the semiconductor device comprises:

[0021] an interlayer insulation film placed on the insulation film forseparating components and the first conductive layer, and

[0022] a second conductive layer placed on the interlayer insulationfilm,

[0023] wherein the first conductive layer is substantially formed onlywithin the component forming region, and

[0024] wherein the first conductive layer and the second conductivelayer are substantially connected only within the component formingregion.

[0025] In accordance with characteristics of the present invention,there is provided a wiring method for a semiconductor device comprisingan insulation film for separating components formed on a basesemiconductor layer, wherein wiring is substantially performed using afirst wiring layer only within a component forming region separated bythe insulation film for separating components;

[0026] wiring is performed using a second wiring layer on an interlayerinsulation film formed on the insulation film for separating componentsand the first wiring layer;

[0027] the first wiring layer and the second wiring layer aresubstantially connected only within the component forming region.

[0028] The characteristics of the present invention are broadlyindicated as noted above, but the structure, contents, object, andfeatures will be clearer through reference to the figures and accordingto the following disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 conceptually illustrates a flat structure of asemiconductor 30 which is a semiconductor device according to anembodiment of the present invention and comprising a transistor 31;

[0030]FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 1;

[0031]FIG. 3 conceptually illustrates a flat structure of asemiconductor device 70 which is a semiconductor device according toanother embodiment of the present invention;

[0032]FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. 3;

[0033]FIG. 5 conceptually illustrates a flat structure of asemiconductor device 80 which is a semiconductor device according toanother embodiment of the present invention;

[0034]FIG. 6 conceptually illustrates a flat structure of asemiconductor device 90 which is a semiconductor device according toanother embodiment of the present invention;

[0035]FIG. 7 is a cross-sectional view taken along line 7-7 of FIG. 6;

[0036]FIG. 8 conceptually illustrates a flat structure of asemiconductor device comprising a conventional MOS type field effecttransistor; and

[0037]FIG. 9 is a cross-sectional view taken along line 9-9 of FIG. 8.

DESCRIPTION OF THE EMBODIMENTS

[0038]FIG. 1 conceptually illustrates a flat structure of asemiconductor device 30 which is a semiconductor device according to anembodiment of the present invention and which comprises a transistor 31(semiconductor component). FIG. 2 is a cross-sectional view taken alongline 2-2 of FIG. 1.

[0039] As shown in FIG. 1, the semiconductor device 30 comprises thetransistor 31 and a transistor 33. The transistor 31 is an N channel MOStype field effect transistor which controls the current flowing betweensource S1 and drain D1 according to the voltage applied to a gateelectrode 42 which will be described later. The transistor 33 is also aMOS type field effect transistor. In this embodiment, both transistorsare low withstand voltage transistors.

[0040] As shown in FIG. 2, the transistor 31 is formed in a componentforming region 32, and the transistor 33 is formed in another componentforming region 34. The component forming region 32 and the componentforming region 34 are separated by a field oxide film for separatingcomponents 38 (insulation film for component separation) which is formedon a P type (second conductive type) semiconductor substrate 36 (basesemiconductor layer). The field oxide film 38 can be formed, forexample, using the LOCOS (Local Oxidation of Silicon) method.

[0041] The transistor 31 formed on the component forming region 32comprises N type (first conductive type) source S1 (second semiconductorregion) and N type drain D1 (first semiconductor region) both formedwithin the semiconductor substrate 36 with a specified distanceinterposed between (see FIG. 1). In the semiconductor substrate 36, theregion sandwiched between source S1 and drain D1 is a channel formingregion CH1.

[0042] A gate electrode 42 (first conductive layer, first wiring layer)is formed on the channel forming region CH1 via gate oxide film 40 (gateinsulation film). The gate electrode 42 is composed from polysilicon. Aninterlayer film 44 (interlayer insulation film) is formed on the gateelectrode 42 and the field oxide film 38. A gate-use aluminum wiring 48(second conductive layer, second wiring layer) is formed on theinterlayer film 44.

[0043] The gate electrode 42 and the aluminum wiring 48 are connectedvia contact hole 46 formed in the interlayer film 44.

[0044] A source aluminum wiring (not illustrated) and a drain aluminumwiring (not illustrated) of the transistor 31 are formed on theinterlayer film 44. The source aluminum wiring is connected to source S1via contact hole 50 (see FIG. 1) which is formed in the interlayer film44. Similarly, the drain aluminum wiring is connected to drain D1 viacontact hole 52 (see FIG. 1) formed in the interlayer film 44.

[0045] In contrast, as shown in FIG. 2, the transistor 33 formed in thecomponent forming region 34 comprises N type source S2 and drain D2formed within the semiconductor substrate 36 with a specified distancebetween them. In the semiconductor substrate 36, the region sandwichedbetween source S2 and drain D2 is a channel forming region CH2.

[0046] A gate electrode 56 is formed on the channel forming region CH2via gate oxide film 54. As with the transistor 31, the interlayer film44 covers the top of the gate electrode 56.

[0047] A source aluminum wiring 62 and a drain aluminum wiring 64 of thetransistor 33 are formed on the interlayer film 44. The source aluminumwiring 62 is connected to source S2 via contact hole 58 formed in theinterlayer film 44. Similarly, the drain aluminum wiring 64 is connectedto drain D2 via contact hole 60 formed in the interlayer film 44.

[0048] As shown in FIG. 2, this embodiment is structured such that thegate electrode 42 is formed only within the component forming region 32.Therefore, the gate electrode 42 is not substantially formed on thefield oxide film 38. Because of this, there is very low risk ofinversion of the surface of the semiconductor substrate 36 which isunder the field oxide film 38 due to the voltage of the gate electrode42.

[0049] The invention is constructed so that the gate electrode 42 andthe aluminum wiring 48 are connected within the component forming region32. Therefore, there is a low possibility of inversion of the surface ofthe semiconductor substrate 36 which is under the field oxide film 38due to the voltage of the concerned connection part.

[0050] Furthermore, part of the aluminum wiring 48 is formed on thefield oxide film 38 (see FIG. 1), but because the interlayer film 44 isbetween the aluminum wiring 48 and the field oxide film 38, there islittle risk of inversion of the surface of the semiconductor substrate36 under the field oxide film 38 due to the voltage of the aluminumwiring 48.

[0051] Thus, it is possible to separate components without increasingoverall length L1 of the field oxide film 38. Therefore, it is notnecessary to expand the distance between the transistor 31 and thetransistor 33. It is also possible to separate components withoutincreasing the film thickness of the field oxide film 38 or increasingthe concentration of channel stop ions implanted into the surface of thesemiconductor substrate 36 which is under the field oxide film 38.

[0052] In other words, it is easy to separate components without makingsacrifices in terms of items such as level of integration, withstandvoltage, or manufacturing cost.

[0053] In this embodiment, the film thickness of the field oxide film 38is approximately 5000 Å, the film thickness of the gate electrodes 42and 56 is approximately 3000 Å, and the film thickness of the aluminumwiring 48, 62, and 64 is approximately 10000 Å.

[0054] The concentration of boron (B) which is the channel stop ionimplanted into the surface of the semiconductor substrate 36 which isunder the field oxide film 38 is 5×10¹³ cm⁻², and the implantationenergy is 30 KeV.

[0055] As shown in FIG. 1, with this embodiment, the device isstructured such that the width in the channel length direction (Ydirection in the figure) for an area 42 a near the connection with thealuminum wiring 48 (i.e. near the contact hole 46) in the gate electrode42 is wider than the width of other areas. This allows a margin to besecured when connecting the gate electrode 42 and the aluminum wiring 48(i.e. the position matching margin of the contact hole 46).

[0056] Therefore, even with a low withstand voltage transistor with arelatively small channel length, it is possible to secure a contactbetween the gate electrode 42 and the aluminum wiring 48 withoutsubstantially changing the channel length.

[0057] Next, FIG. 3 conceptually illustrates a flat structure of asemiconductor device 70 comprising a transistor 71 (semiconductorcomponent) which is a semiconductor device according to anotherembodiment of the present invention. FIG. 4 is a cross-sectional viewtaken along line 4-4 of FIG. 3.

[0058] As shown in FIG. 4, this semiconductor device 70 has almost thesame structure as the semiconductor device 30 described above, butcomprises the transistor 71 instead of the transistor 31 (see FIG. 2).Similar to the transistor 31, the transistor 71 is a MOS type fieldeffect transistor.

[0059] However, in contrast to the transistor 31, for the transistor 71,the film thickness of an oxide film 74 (an insulation film thatcontinues the gate insulation film and that is beneath the connectionarea between the first semiconductor layer and the second semiconductorlayer) near the connecting area of the gate electrode 42 and thealuminum wiring 48 (i.e. directly beneath the contact hole 46) isstructured so as to be thicker than the film thickness of the gate oxidefilm 40 in areas other than the oxide film 74.

[0060] By using such a structure, it is possible to more securelyprevent etching damage to the gate oxide film 40 and the channel formingregion CH1 under this gate oxide film 40 when opening the contact hole46 in the interlayer film 44 using, for example, the RIE (reactive ionetching) method.

[0061] The oxide film 74 with this thick film thickness can be formedusing a method such a the LOCOS method described above for the sameprocess as that used to form the field oxide film 38. By doing this, itis possible to form the oxide film 74 with a greater film thicknesswithout increasing the number of processes.

[0062] Next, FIG. 5 conceptually illustrates a flat structure of asemiconductor device 80 comprising a transistor 81 (semiconductorcomponent), which is a semiconductor device made according to anotherembodiment of the present invention. The cross-sectional structure ofthe semiconductor device 80 is the same as that shown in FIG. 2, so isnot noted here.

[0063] As shown in FIG. 5, this semiconductor device 80 has almost thesame structure as that of the semiconductor device 30 described above,but comprises the transistor 81 which is a high withstand voltage typeinstead of the transistor 31 (see FIG. 1). In contrast to the transistor31, for the transistor 81, the width in the channel length direction (Ydirection in the figure) of the area near the connection area with thealuminum wiring 48 (i.e. near the contact hole 46) is the same as thewidth of other areas.

[0064] This is due to the following. Similar to the transistor 31, thetransistor 81 is a MOS type field effect transistor, but in contrast tothe transistor 31, it is a high withstand voltage type transistor.Therefore, for the transistor 81, the width in the channel lengthdirection of a gate electrode 84 is broader than that of the transistor31.

[0065] Thus, in contrast to the gate electrode 42 of the transistor 31,even if the width of the channel length direction in the area near thecontact hole 46 is the same as the width of other parts, it is possibleto secure a position matching margin for the contact hole 46.

[0066] In this way, when the width of the channel length direction ofthe gate electrode 84 is wide as it is with the high withstand voltagetype transistor 81, it is possible to connect to the aluminum wiring 48without changing the width of the channel length direction of the gateelectrode 84, so there is no need to increase the planar projection areaof the transistor 81. Therefore, it is possible to suppress the decreasein level of integration.

[0067] Also, for this semiconductor device 80, the high withstandvoltage transistor 81 and the low withstand voltage transistor 33 aremixed, but the film thickness for the field oxide film 38 of the highwithstand voltage transistor 81 and the film thickness of the fieldoxide film 38 of the low withstand voltage transistor 33 are both of thesame thin film thickness.

[0068] This is because by using this invention, even with the fieldoxide film 38 of a thin film thickness such as that used with the lowwithstand voltage transistor 33, it is possible to separate componentsfor the high withstand voltage transistor 81.

[0069] Therefore, there is no need to increase the field oxide filmthickness for the low withstand voltage transistor 33 to match thethickness of the field oxide film of the high withstand voltagetransistor 81, and it is also not necessary to change the film thicknessof the field oxide film 38 between the high withstand voltage transistor81 and the low withstand voltage transistor 33.

[0070] Specifically, even for a semiconductor device which mixes highwithstand voltage transistors and low withstand voltage transistors aswith E²PROM and various drivers, it is possible to separate componentseasily without sacrificing items such as level of integration, withstandvoltage, or manufacturing cost.

[0071] Even for the transistor 81, as with the transistor 71 (see FIG.4) described above, it is possible to make the structure such that thefilm thickness of the oxide film (not illustrated, see the oxide film 74in FIG. 4) near the connection area (i.e. immediately beneath thecontact hole 46) of the gate electrode 42 and the aluminum wiring 48 isthicker than the film thickness of the gate oxide film of parts otherthan the concerned oxide film (not illustrated, see the gate oxide film40 in FIG. 4).

[0072] Next, FIG. 6 conceptually illustrates a flat structure of asemiconductor device 90 comprising a transistor 91 (semiconductorcomponent), which is a semiconductor device according to yet anotherembodiment of the present invention. FIG. 7 shows a cross-sectional viewtaken along line 7-7 of FIG. 6.

[0073] As shown in FIG. 6, this semiconductor device 90 hasapproximately the same structure as that of the semiconductor device 80described above, but comprises the transistor 91 instead of thetransistor 81 (see FIG. 5). Similar to the transistor 31, the transistor91 is a high withstand voltage MOS type field effect transistor.

[0074] However, in contrast to the transistor 81, the transistor 91 isstructured such that the substantially flat shape of a channel formingregion CH3, a gate oxide film 94, and a gate electrode 96 is made into aring shape that circles drain D3, while the substantially flat shape ofsource S3 is made into a ring shape that circles the channel formingregion CH3.

[0075] By using such a structure, drain D3 is isolated from the fieldoxide film 38. Thus, there is no occurrence of a decrease in the drainwithstand voltage due to the effect of the channel stop ions implantedinto the surface of the semiconductor substrate 36 which is below thefield oxide film 38. In other words, it is possible to obtain atransistor with higher withstand voltage.

[0076] By using this invention, even with the transistor 91 which has ahigher withstand voltage, specifically the transistor 91 for which ahigher voltage is applied to the gate electrode 96, it is possible toseparate components easily without sacrificing items such as level ofintegration, withstand voltage, and manufacturing cost.

[0077] As shown in FIG. 7, a source-use aluminum wiring 104 of thetransistor 91 is formed on the interlayer film 44. The source-usealuminum wiring 104 is connected to source S3 via contact hole 102 whichis formed in the interlayer film 44.

[0078] A drain-use aluminum wiring (not illustrated) of the transistor91 is also formed in the interlayer film 44. The drain-use aluminumwiring its connected to drain D3 (see FIG. 6) via contact hole 106 whichis formed in the interlayer film 44.

[0079] As shown in FIG. 6, the structure of the transistor 91 is suchthat the substantially flat shape of the channel forming region CH3, thegate oxide film 94, and the gate electrode 96 is made into a rectangularring shape that circles drain D3, and the corner of the rectangular ringshaped gate electrode 96 is formed so that the gate electrode 96 and analuminum wiring 100 are connected at the corner.

[0080] Therefore, by connecting the gate electrode 96 and the aluminumwiring 100 at the rectangular ring corner with a small current flowingbetween drain D3 and source S3, it is possible to connect the gateelectrode 96 and the aluminum wiring 100 while minimizing the effect ofthe concerned current.

[0081] Even when the width required for connecting the gate electrode 96and the aluminum wiring 100 is wider than the width of the gateelectrode 96, by connecting the gate electrode 96 and the aluminumwiring 100 at the corner, it is possible to keep the increase in thearea of the gate electrode 96 for the connecting area to a minimum.Therefore, it is possible to minimize the decrease in level ofintegration.

[0082] For the transistor 91 shown in FIG. 7 as well, as with thetransistor 71 (see FIG. 4) described above, it is possible to have astructure so that the film thickness of the oxide film near theconnecting area of the gate electrode 96 and the aluminum wiring 100(i.e. directly beneath a contact hole 98) is thicker than the filmthickness of the gate oxide film 94 that is in areas other than theconcerned oxide film.

[0083] In the embodiments described above, we explained examples ofusing the present invention in semiconductor devices comprising only lowwithstand voltage transistors (semiconductor components) andsemiconductor devices with a mixture of low withstand voltagetransistors and high withstand voltage transistors, but the presentinvention can also be used for semiconductor devices comprising onlyhigh withstand voltage transistors.

[0084] Also, in the embodiments described above, we explained an exampleof a semiconductor device comprising an N channel MOS type field effecttransistor, but the present invention is not limited thereto. Forexample, the present invention can also be used for semiconductordevices comprising P channel MOS type field effect transistors.

[0085] Also, for example, the present invention can be used forsemiconductor devices comprising MOS type field effect transistors whichhave an LDD (lightly-doped drain), semiconductor devices comprising MOStype field effect transistors which have DD (double drain), andsemiconductor devices comprising DMOS (double diffusion MOS type fieldeffect transistors).

[0086] Further, for example, the present invention can be used forsemiconductor devices comprising memory cells which have floating gatessuch as E²PROM, semiconductor devices comprising bipolar typetransistors, semiconductor devices comprising capacitors, andsemiconductor devices comprising resistor components.

[0087] The present invention is such that a semiconductor devicecomprises an interlayer insulation film placed on an insulation film forseparating components and on a first conductive layer, and a secondconductive layer placed on the interlayer insulation film, and in thatthe first conductive layer is substantially formed only within acomponent forming region and that the first conductive layer and thesecond conductive layer are substantially connected only within thecomponent forming region.

[0088] Therefore, the first conductive layer is substantially not formedon the insulation film for separating components, so there is littlepossibility of inversion of the surface of the base semiconductor layerwhich is under the insulation film for separating components due to thevoltage of the first conductive layer.

[0089] Also, even when a second conductive layer is formed on aninsulation film for separating components, there is an interlayerinsulation film between the second conductive layer and the insulationfilm for separating components, so there is little possibility ofinversion of the surface of the base semiconductor layer that is underthe insulation film for separating components due to the voltage of thesecond conductive layer.

[0090] Furthermore, the first conductive layer and the second conductivelayer are substantially connected only within the component formingregion, so there is little possibility of inversion of the surface ofthe base semiconductor layer that is under the insulation film forseparating components due to the voltage of the connection area.

[0091] Therefore, it is possible to separate components withoutincreasing the overall length of the insulation film for separatingcomponents, increasing the film thickness of the insulation film forseparating components, or increasing the concentration of impurities inthe surface of the base semiconductor layer that is under the insulationfilm for separating components. In other words, it is possible toseparate components easily without sacrificing items such as level ofintegration, withstand voltage, and manufacturing cost.

[0092] The present invention is such that the semiconductor componentscomprise a first conductive type first semiconductor region, a firstconductive type second semiconductor region wherein the secondsemiconductor region is formed separated a specified distance from thefirst semiconductor region, a second conductive type channel formingregion formed between the first semiconductor region and the secondsemiconductor region, a gate insulation film formed on the channelforming region, and a first conductive layer formed on the gateinsulation film.

[0093] Therefore, even for a semiconductor device comprising asemiconductor component that controls the current flowing between afirst semiconductor region and a second semiconductor region accordingto the voltage applied to a first conductive layer such as with a MOStype field effect transistor, for example, it is possible to separatecomponents easily without sacrificing items such as level ofintegration, withstand voltage, and manufacturing cost.

[0094] The present invention is such that the substantially flat shapeof the channel forming region, gate insulation film, and firstconductive layer is a ring shape that circles a first semiconductorregion, and the substantially flat shape of the second semiconductorregion is a ring shape that circles the channel forming region.

[0095] Therefore, even for a semiconductor device comprising asemiconductor component for which a high voltage is applied to the firstconductive layer such as with a high withstand voltage MOS type fieldeffect transistor, for example, it is possible to separate componentseasily without sacrificing items such as level of integration, withstandvoltage, and manufacturing cost.

[0096] The present invention is such that the substantially flat shapeof the channel forming region, gate insulation film, and firstconductive layer is a rectangular ring shape that circles a firstsemiconductor region, and in that the first conductive layer and secondconductive layer are connected at the corner of the rectangular ringshaped first conductive layer.

[0097] Therefore, by connecting the first conductive layer and secondconductive layer at the corner of the rectangular ring shape which has asmall current flowing between the first semiconductor region and secondsemiconductor region, it is possible to connect the first conductivelayer and second conductive layer while minimizing the effect on thecurrent flowing between the first semiconductor region and secondsemiconductor region.

[0098] Also, even when the width needed to connect the first conductivelayer and the second conductive layer is wider than the width of thefirst conductive layer, it is possible to keep the increase in the areaof the first conductive layer to a minimum. Therefore, it is possible tosuppress the decrease in level of integration.

[0099] The present invention is such that the film thickness of theinsulation film that is continuous with the gate insulation film andthat is under the connecting area of the first conductive layer andsecond conductive layer is thicker than the film thickness of the gateinsulation film.

[0100] Therefore, it is possible to suppress the effect on the layerunder the gate insulation film due to the connection of the firstconductive layer and the second conductive layer.

[0101] The present invention is such that the width, which is the widthin the channel length direction of the first conductive layer, for thearea that corresponds to the connection area with the second conductivelayer, is wider than the width of areas other than areas that correspondto the concerned connection area.

[0102] Therefore, even with a semiconductor component for which thechannel length is relatively small, it is possible to secure aconnection area for the first conductive layer and second conductivelayer without substantially changing the channel length.

[0103] The present invention is such that the semiconductor componentsare high withstand voltage semiconductor components, and that theconcerned semiconductor device also comprises low withstand voltagesemiconductor components in addition to the concerned high withstandvoltage semiconductor components.

[0104] Therefore, it is possible to form insulation film for separatingcomponents that are high withstand voltage semiconductor components atthe same film thickness as the insulation film for separating componentsthat are low withstand voltage semiconductor components which have athin film thickness. Therefore, it is not necessary to increase the filmthickness of insulation film for separating components for allsemiconductor components or to change the film thickness of theinsulation film for separating components between high withstand voltagesemiconductor components and low withstand voltage semiconductorcomponents.

[0105] Specifically, even for a semiconductor device which mixes highwithstand voltage semiconductor components and low withstand voltagesemiconductor components such as E²PROM or various drivers, for example,it is possible to separate components easily without sacrificing itemssuch as level of integration, withstand voltage, and manufacturing cost.

[0106] The present invention is such that wiring is substantiallyperformed using a first wiring layer only in the component formingregion separated by an insulation film for separating components, wiringis performed using a second wiring layer on the interlayer insulationfilm formed on the insulation film for separating components and thefirst wiring layer, and that substantially the first wiring layer andsecond wiring layer are connected only within the component formingregion.

[0107] Therefore, wiring using a first wiring layer is substantiallyperformed only within the component forming region, so there is littlepossibility of the occurrence of inversion of the surface of the basesemiconductor layer under the insulation film for separating componentsdue to the voltage of the first wiring layer.

[0108] Also, even when a second wiring layer is formed on the insulationfilm for separating components, there is an interlayer insulation filmbetween the second wiring layer and the insulation film for separatingcomponents, so there is little possibility of the occurrence ofinversion of the surface of the base semiconductor layer that is beneaththe insulation film for separating components due to the voltage of thesecond wiring layer.

[0109] Also, the first wiring layer and the second wiring layer aresubstantially connected only within the component forming region, sothere is little possibility of the inversion of the surface of the basesemiconductor layer that is beneath the insulation film for separatingcomponents due to the voltage of the concerned connection area.

[0110] Therefore, it is possible to perform the desired wiring withoutregard to being on the inside or outside of the component formingregion, and it is possible to separate components easily withoutsacrificing items such as level of integration, withstand voltage, andmanufacturing cost.

[0111] In the above description, we explained the embodiments that arepreferable for the present invention, but the terms used are not used tolimit the invention, but are rather used for descriptive purposes, andit is possible to make modifications within the scope of the attachedclaims without straying from the scope or spirit of the presentinvention.

1. A semiconductor device, comprising: a base semiconductor layer; aninsulation film for separating components formed on the basesemiconductor layer; and a semiconductor component which is formed onthe base semiconductor layer in a component forming region separated bythe insulation film for separating components, the semiconductorcomponent having a first conductive layer; wherein the semiconductordevice comprises: an interlayer insulation film placed on the insulationfilm for separating components and the first conductive layer; and asecond conductive layer placed on the interlayer insulation film;wherein the first conductive layer is substantially formed only withinthe component forming region; and wherein the first conductive layer andthe second conductive layer are substantially connected only within thecomponent forming region.
 2. The semiconductor device according to claim1 , wherein the semiconductor component is a high withstand voltagesemiconductor component; the semiconductor device comprising a lowwithstand voltage semiconductor component in addition to the highwithstand voltage semiconductor component.
 3. The semiconductor deviceaccording to claim 1 , wherein the semiconductor component comprises: afirst semiconductor region of a first conductive type; a secondsemiconductor region of a first conductive type, wherein the secondsemiconductor region is formed separate from the first semiconductorregion by a specified distance; a second conductive type channel formingregion formed between the first semiconductor region and the secondsemiconductor region; a gate insulation film formed on the channelforming region; and the first conductive layer formed on the gateinsulation film.
 4. The semiconductor device according to claim 3 ,wherein a film thickness of an insulation film under a connecting areaof the first conductive layer and the second conductive layer, theinsulation film being continuous with the gate insulation film, isthicker than a film thickness of the gate insulation film.
 5. Thesemiconductor device according to claim 3 , wherein a width of an areathat corresponds to the portion connecting with the second conductivelayer, the width being in the channel length direction of the firstconductive layer, is wider than the width of areas other than the areacorresponding to the connecting area.
 6. The semiconductor deviceaccording to claim 3 , wherein the semiconductor component is a highwithstand voltage semiconductor component; the semiconductor devicecomprising a low withstand voltage semiconductor component in additionto the high withstand voltage semiconductor component.
 7. Thesemiconductor device according to claim 3 , wherein substantially flatshape of the channel forming region, the gate insulation film, and thefirst conductive layer is in a shape of a ring that surrounds the firstsemiconductor region; substantially flat shape of the secondsemiconductor region is in a shape of a ring that surrounds the channelforming region.
 8. The semiconductor device according to claim 7 ,wherein a film thickness of an insulation film under a connecting areaof the first conductive layer and the second conductive layer, theinsulation film being continuous with the gate insulation film, isthicker than a film thickness of the gate insulation film.
 9. Thesemiconductor device according to claim 7 , wherein a width of an areathat corresponds to the portion connecting with the second conductivelayer, the width being in the channel length direction of the firstconductive layer, is wider than the width of areas other than the areacorresponding to the connecting area.
 10. The semiconductor deviceaccording to claim 7 , wherein the semiconductor component is a highwithstand voltage semiconductor component; the semiconductor devicecomprising a low withstand voltage semiconductor component in additionto the high withstand voltage semiconductor component.
 11. Thesemiconductor device according to claim 7 , wherein the substantiallyflat shape of the channel forming region, the gate insulation film, andthe first conductive layer is in a rectangular ring shape that surroundsthe first semiconductor region; the first conductive layer and thesecond conductive layer is connected at a corner of the rectangular ringshaped first conductive layer.
 12. The semiconductor device according toclaim 11 , wherein a film thickness of an insulation film under aconnecting area of the first conductive layer and the second conductivelayer, the insulation film being continuous with the gate insulationfilm, is thicker than a film thickness of the gate insulation film. 13.The semiconductor device according to claim 11 , wherein a width of anarea that corresponds to the portion connecting with the secondconductive layer, the width being in the channel length direction of thefirst conductive layer, is wider than the width of areas other than areacorresponding to the connecting area.
 14. The semiconductor deviceaccording to claim 11 , wherein the semiconductor component is a highwithstand voltage semiconductor component; the semiconductor devicecomprising a low withstand voltage semiconductor component in additionto the high withstand voltage semiconductor component.
 15. A wiringmethod for a semiconductor device comprising insulation film forseparating components formed on a base semiconductor layer, whereinwiring is substantially performed using a first wiring layer only withina component forming region separated by the insulation film forseparating components; wiring is performed using a second wiring layeron an interlayer insulation film formed on the insulation film forseparating components and the first wiring layer; the first wiring layerand the second wiring layer are substantially connected only within thecomponent forming region.